Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

This application is a continuation of application Ser. No. 243,607,filed on Sep. 13, 1988, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice. In particular, it relates to techniques which are effective whenapplied to a semiconductor integrated circuit device having at least twolayers of aluminum wiring, more desirably, a semiconductor integratedcircuit device including a DRAM (Dynamic Random Access Memory) having atleast two layers of aluminum wiring.

In recent years, DRAMs of 1 [Mbit] or 4 [Mbits] each having two layersof aluminum wiring have been actively developed. They are described in,for example, "Denshi-Zairyo (Electronics Materials)," January 1986, pp.39-44, and "Nikkei Microdevices, Extra Issue No. 1" issued by NikkeiMcGraw-Hill Inc., May 1987, pp. 149-164. In any of these DRAMs, thesecond layer of aluminum wiring is used as shunt wiring for lowering theresistance of a word line made of a poly-cide. That is, the word line ofthe poly-cide and the second layer of aluminum wiring are laid inparallel and are connected to each other at predetermined intervals.

SUMMARY OF THE INVENTION

The memory cell of the above-mentioned DRAM for storing information of 1[bit] is constructed of a series circuit consisting of a memory cellselecting MISFET and an information storing capacitor. The chip of theDRAM is mainly sealed with an SOJ (Small Out-line J-lead Package) or aZIP (Zigzag In-line Package).

Resin-encapsulated products of this type have the sizes of packages andthe arrangements of external leads stipulated on the basis of standards.Therefore, the arrangement of the individual circuits of the DRAM isdetermined to some extent in accordance with the stipulations.

A DRAM under development by the inventors has a rectangular chip. Amemory cell array is arranged at the central part of the rectangularchip. The memory cell array occupies the greater part of the area of therectangular chip. Peripheral circuits for driving the DRAM arerespectively arranged on the opposing shorter latus sides of therectangular chip. The peripheral circuits arranged on one shorter latusside (the upper latus side), principally include reference clock signalgenerators such as a row address strobe (RAS)-group circuit and a columnaddress strobe (CAS)-group circuit. External terminals (bonding pads)for reference clock signals are arranged near the reference clock signalgenerators. The peripheral circuits arranged on the other shorter latusside (the lower latus side), principally include address-group circuitssuch as an X-address buffer and a Y-address buffer. Likewise, externalterminals for address signals are arranged near the address-groupcircuits.

The acceptance of the address signals of the address-group circuits iscontrolled on the basis of the reference clock signals formed by thereference clock signal generators. To this end, the reference clocksignal generators and the address-group circuits which are arrangedalong the respective opposing shorter latera of the rectangular chip areconnected by reference clock signal-wiring leads. The reference clocksignal-wiring leads are arranged in the small areas between the longerlatera of the rectangular chip and the longer edges of the memory cellarray so as to extend along these longer latera of the chip. Each of thereference clock signal-wiring leads is formed of the first layer orsecond layer of aluminum wiring. In case of the DRAM having a largememory capacity of 4 [Mbits], the reference clock signal-wiring leadneeds to be laid from one shorter latus side to the other shorter latusside of the rectangular chip with a great wiring length of about 10[mm]. In consequence, the reference clock signal is conspicuouslydelayed to decrease the margins of an address setup time and an addresshold time. Another problem is that, since the decreases in the marginsincur increase in an access time, the operating speed of the DRAM islowered.

Besides, in the DRAM having the two layers of aluminum wiring asdescribed above, the first layer of aluminum wiring and the secondlayers of aluminum wiring have equal thicknesses. In this case, at apart where the first and second layers of aluminum wiring intersect, astep ascribable to the first layer of aluminum wiring is large. Thisleads to the problem that the step coverage of the second layer ofaluminum wiring at the intersection part thereof with the first layer ofaluminum wiring is inferior, so the intersection part is liable tobreak.

An object of the present invention is to provide a technique which canheighten the operating speed of a semiconductor integrated circuitdevice including a DRAM.

Another object of the present invention is to provide a technique whichcan accomplish the first-mentioned object by heightening the propagatingspeed of a reference clock signal.

Another object of the present invention is to provide a technique whichcan prevent the breaking of the second layer of aluminum wiring at astepped part ascribable to the first layer of aluminum wiring.

The above and other objects and novel features of the present inventionwill become apparent from the description of this specification and theaccompanying drawings.

Typical aspects of performance of the present invention are brieflysummarized as follows:

In a DRAM, a reference clock signal-generator and an address-groupcircuit which are respectively arranged on the opposing shorter latussides of a rectangular chip are connected by a reference clocksignal-wiring lead of double layer-wiring structure which extends alongthe longer latus of the rectangular chip and the two layers of which areshort-circuited.

In addition, the thickness of the first layer of aluminum wiring isrendered smaller than that of the second layer of aluminum wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 is a chip layout plan of a DRAM which is an embodiment of thepresent invention;

FIG. 2 is an enlarged block diagram of the peripheral circuits of theDRAM;

FIGS. 4 thru 10 are equivalent circuit diagrams of the essentialportions of the DRAM;

FIG. 11 is an enlarged plan view of a part indicated by symbol I in FIG.2;

FIG. 12 is an enlarged plan view of a part indicated by symbol II inFIG. 2;

FIG. 13 is an enlarged sectional view of the essential portions of thereference clock signal-wiring of the DRAM;

FIG. 14 is a plan view showing the layout of a data line prechargecircuit portion in a peripheral circuit area;

FIG. 15 is an equivalent circuit diagram of the data line prechargecircuit portion shown in FIG. 14;

FIG. 16 is a plan view showing the layout of an I/O transfer circuitportion;

FIG. 17 is an equivalent circuit diagram of the I/O transfer circuitportion shown in FIG. 16;

FIG. 18 is a plan view showing the cross-under portion between powersource wiring and signal wiring; and

FIG. 19 is a plan view showing the layout of any CMOS inverter circuitsin the peripheral circuit area.

DETAILED DESCRIPTION OF THE INVENTION

A DRAM which is one embodiment of the present invention is illustratedin FIG. 1 (a chip layout plan) and FIG. 2 (an enlarged block diagram ofperipheral circuits).

As shown in FIG. 1, a DRAM 1 is constructed on a semiconductor substratewhich is made of single-crystal silicon. The DRAM 1 is configured of 4[Mbits]×1 [bit] (or 1 [Mbit]×4 [bits]).

By way of example, the DRAM 1 is formed of a rectangular chip havingshorter latera of 6.38 [mm] and longer latera of 17.38 [mm]. It isencapsulated with a resin by the use of an SOJ, a ZIP or the like thoughnot depicted.

As shown in FIGS. 1 and 2, external terminals (bonding pads) 2 arearranged at the outermost peripheral parts of the DRAM 1 and along partsof the shorter latera and longer latera of the rectangular chip. Theexternal terminals 2 arranged on one shorter latus side (the uppershorter latus side) are respectively used for an address signal A₁₀, arow address strobe signal RAS, a write enable signal WE, a data inputsignal Din, a data output signal Do, a column address strobe signal CAS,an address signal A₉, a function pad FP₀, and a reference voltageV_(ss). The external terminals 2 arranged on the other shorter latusside (the lower shorter latus side) are respectively used for addresssignals A₀ -A₈, a power source voltage V_(cc), and a function pad FP₁.

The external terminals 2 to be used as the function pads FP₀ and FP₁ canbe changed-over to a page mode, a nibble mode and a static column modewhen pieces of bonding wire are to be connected thereto. The groundpotential, 0 [V] of circuitry, for example, is applied as the referencevoltage V_(ss). The operating potential, 5 [V] of the circuitry, forexample, is applied as the power source voltage V_(cc). Each of theexternal terminals 2 for the reference voltage V_(ss) and the externalterminals 2 for the power source voltage V_(cc) is subjected toso-called double bonding or triple bonding in which a plurality ofbonding wire pieces are connected. This bonding method is adopted for ameasure against noise.

A memory cell array MARY is arranged at the central part of the DRAM 1.The memory cell array MARY is broadly divided into four. Each of thedivisional memory cell arrays MARY is constructed so as to have a largememory capacity of 1 [Mbit]. The divided individual memory cell arrayMARY is subdivided into four. As shown in FIGS. 1 and 2, senseamplifiers SA are arranged at the central part of each of the subdividedmemory cell arrays MARY and along the longer latus of the rectangularchip (in the row direction of the DRAM). Complementary data linesextending in the memory cell array MARY in the column direction of theDRAM are connected to the sense amplifiers SA. That is, the DRAM 1 isconstructed in accordance with the folded bit line organization.

Y-decoders YDec are respectively arranged between the two, right andleft memory cell arrays MARY on the upper latus side as broadly dividedand between the two, right and left memory cell arrays MARY on the lowerlatus side. X-decoders XDec and word driver and word latch circuits XLare respectively arranged between the two, upper and lower memory cellarrays MARY on the left side and between the two, upper and lower memorycell arrays MARY on the right side. Word clear circuits WC are arrangedat the end parts of the memory cell arrays MARY opposite to theX-decoders XDec.

Each memory cell array MARY is constructed by arranging a plurality ofmemory cells, not shown, in the shape of a matrix. The memory cell isconstructed of a series circuit consisting of a memory cell selectingMISFET, and an information storing capacitor which is connected to onesemiconductor region of the MISFET. The memory cell selecting MISFET isformed into the n-channel type. The information storing capacitor isformed as a stacked structure in which a lower-layer electrode(polycrystalline silicon film), a dielectrics film, and an upper-layerelectrode (polycrystalline silicon film) are successively stacked on thesilicon substrate. A power source voltage, 1/2 V_(cc) is applied to theupper-layer electrode. The power source voltage, 1/2 V_(cc) is theintermediate potential (about 2.5 [V]) between the power source voltageV_(cc) and the reference voltage V_(ss).

The complementary data lines are connected to the other semiconductorregion of the memory cell selecting MISFET of the memory cell. Thecomplementary data lines are connected to the sense amplifiers SA asdescribed before, and they are also connected to an input/output signalline (I/O line) through an input/output selecting MISFET (Y-switch). Theinput/output selecting MISFET is connected to the Y-decoder YDec througha Y-select signal line. The gate electrode of the memory cell selectingMISFET is connected to a word line. The word lines are extended in therow direction of the memory cell array MARY, and are connected to theX-decoder XDec through the word driver circuit.

As shown in FIGS. 1 and 2, peripheral circuits which principally includereference clock signal generators are arranged on one shorter latus sideof the DRAM 1. That is, on one shorter latus side, there are arrangedthe major, reference clock signal generators of the first-stage circuitof a row address strobe-group circuit (RAS-group circuit) RAS and thefirst-stage circuit of a column address strobe-group circuit (CAS-groupcircuit) CAS, data input/output circuits (D_(in) /D_(out) circuits)D_(in) and D_(out), a write enable circuit (WE circuit) WE, anupper-latus address circuit ADU, main amplifiers MA1-MA8, and powersource circuits SAD for the sense amplifiers.

The first-stage circuit of the row address strobe-group circuit RAS,which is the reference clock signal generator, is arranged near theexternal terminal 2 for the row address strobe signal RAS in order toreduce the delay of the signal. Likewise, the first-stage circuit of thecolumn address strobe-group circuit CAS is arranged near the externalterminal 2 for the column address strobe signal CAS.

The row address strobe signal RAS is used in all the peripheral circuitsof the peripheral circuits on one shorter latus side and the peripheralcircuits on the other shorter latus side. Since the external terminals 2for the row address strobe signal RAS are arranged on one shorter latusside as described before, the first-stage circuit of the row addressstrobe-group circuit RAS and generators for the RAS-group referenceclock signals to be used on the shorter latus side are arranged on oneshorter latus side.

Peripheral circuits which principally include address-group circuits arearranged on the other shorter latus side of the DRAM 1. That is, on theother shorter latus side, there are arranged the address-group circuitsof an X-address buffer XAB and a Y-address buffer YAB, the next-stagecircuits of the row address strobe-group circuit RAS, and an X-generatorcircuit JG. Since the external terminals 2 for the address signals A₀-A₈ are arranged on the other shorter latus side, the address-groupcircuits are arranged near them.

As shown in FIG. 3, the first-stage circuit of the row addressstrobe-group circuit RAS and the generator for the RAS-group referenceclock signal are constructed of a multistage inverter structure in orderto shape waveforms and to intensify driving abilities. The first-stagecircuit of the row address strobe-group circuit RAS produces thereference clock signal (internal clock signal) R1 which has the earliesttiming in the RAS-group reference clock signals. The reference clocksignal R1 is used as a reference clock signal which is input to theclock signal generators arranged on one and the other shorter latussides. Besides, as shown in FIG. 3, the reference clock signal R1 servesto produce the reference clock signal R1U which is used on one shorterlatus side (the upper latus side). Incidentally, in FIG. 3, symbol WKUdenotes a wake-up signal, and symbol RE a RAS end signal.

The reference clock signal R1 produced by the first-stage circuit of therow address strobe-group circuit RAS is transmitted from one shorterlatus side to the other shorter latus side (the lower latus side)through wiring (reference clock signal-wiring) L shown in FIGS. 1 and 2,and is input to the next-stage circuits of the row address strobe-groupcircuit RAS. The next-stage circuits of the row address strobe-groupcircuit RAS are arranged in order to shape the waveform and intensifythe driving ability of the reference clock signal R1 drawn around by thewiring L. As shown in FIG. 4 (an equivalent circuit diagram), thenext-stage circuit of the row address strobe-group circuit RAS isconstructed of a multistage inverter structure. It produces thereference clock signal R2, and the reference clock signal R1D which isused on the other shorter latus side.

As shown in FIG. 5 (an equivalent circuit diagram), the X-address bufferXAB arranged on the shorter latus side is activated by the referenceclock signals R1D and R2 which are produced by the next-stage circuit ofthe row address strobe-group circuit RAS. That is, the reference clocksignals R1D and R2 are used as control signals for accepting the addresssignals A_(i) (i=0, 1, 2, . . . , 8) into the X-address buffer XAB. The

speed of acceptance of the address signals A_(i) is greatly influentialon the operating speed of the DRAM 1 concerning an address setup timeand an address hold time. That is, the access time of the DRAM 1 isrendered shorter as the speed of acceptance of the address signals A_(i)based on the reference clock signals R1D and R2 is higher. The X-addressbuffer XAB produces signals BXi and BXi which are output to theX-decoder XDec. By the way, in FIG. 5, symbolx XL and XL denoteX-address latch signals, symbol C1 the reference clock signal producedby the column address strobe-group circuit CAS, symbol CM a clear modesignal, and symbol ARi a refresh address signal. As shown in FIG. 6 (anequivalent circuit diagram), X-address latch signals XLD and XLD whichare used on the other latus side are produced by the word latch circuitXL on the basis of the reference clock signal R1D.

As shown in FIG. 7 (an equivalent circuit diagram), the column addressstrobe-group circuit CAS is constructed of a multistage inverterstructure likewise to the first-stage circuit of the row addressstrobe-group circuit RAS. The column address strobe-group circuit CASproduces the reference clock signals C0, C1 and C2 which have theearliest timings in the CAS-group reference clock signals. Among thesereference clock signals, the reference clock signal C1 is transmittedfrom one shorter latus side (the upper latus side) to the other shorterlatus side (the lower latus side) through wiring (reference clocksignal-wiring) L and is used for forming a Y-address latch signal YL.

As shown in FIG. 8 (an equivalent circuit diagram), the Y-address bufferYAB arranged on the other shorter latus side is activated by theY-address latch signal YL and the reference clock signal R1D produced bythe next-stage circuit of the row address strobe-group circuit RAS. Thatis, the reference clock signal R1D and the Y-address latch signal YL areused as control signals for accepting the address signals A_(i) (i=0, 1,2, . . . , 8) into the Y-address buffer YAB. The speed of acceptance ofthe address signals A_(i) is greatly influential on the operating speedof the DRAM 1, likewise to the speed of accepting the address signalsA_(i) into the X-address buffer XAB. The Y-address buffer YAB producesoutput signals BYi and BYi to the Y-decoder YDec, and also produces theactivation signal AC of the main amplifier MA as illustrated in FIG. 9(an equivalent circuit diagram). This activation signal AC is producedby the Y-address buffer YAB arranged on the other shorter latus side andis transmitted to one shorter latus side, whereupon it is subjected towaveform shaping and driving ability intensification and then input tothe main amplifier MA as illustrated in FIG. 10 (an equivalent circuitdiagram). Incidentally, symbol CE in FIG. 9 denotes a column enablesignal, and symbol RN in FIG. 10 denotes a RAS normal signal.

As shown in FIG. 1, FIG. 2, FIG. 11 (an enlarged plan view of a partindicated by symbol I in FIG. 2) and FIG. 12 (an enlarged plan view of apart indicated by symbol II in FIG. 2), the DRAM 1 is so constructedthat power source wiring VL and the signal wiring L extend along thelonger latera of the rectangular chip. As illustrated in detail in FIG.11, the power source wiring VL of power source-wiring leads L₂ and L₃and the signal wiring L of signal wiring leads L₄ -L₁₉ are extended fromone shorter latus side to the other shorter latus side along the leftlonger latus of the DRAM 1. As illustrated in detail in FIG. 12, thepower source wiring VL of power source-wiring leads L₃₈ and L₃₉ and thesignal wiring L of signal wiring leads L₂₀ -L₃₇ are extended from oneshorter latus side to the other shorter latus side along the rightlonger latus of the DRAM 1. The power source wiring VL and the signalwiring L are laid by utilizing small areas defined between the longerlatera of the DRAM 1 and the edges of the memory cell array MARY.

Here, wiring leads L₁ and L₄₀ of double-layer wiring structure form aguard ring which is arranged at the outermost periphery of therectangular chip. They prevent impurities from entering the rectangularchip from outside.

The power source voltage V_(cc) is applied to the power source-wiringleads L₂ and L₃, while the reference voltage V_(ss) is applied to thepower source-wiring leads L₃₈ and L₃₉. These leads of the power sourcewiring VL are configured so as to extend outside the leads of the signalwiring L and inside the guard ring. The part of the power source wiringVL arranged along the longer latus of the rectangular chip isconstructed of a double-layer wiring structure in which a first wiringlayer and a second wiring layer are placed one over the other and thenshort-circuited. The DRAM 1 of this embodiment is constructed of adouble-layer aluminum wiring structure, the first and second wiringlayers of which are both made of aluminum wiring leads. In this manner,the part of the power source wiring VL along the longer latus is soformed that the resistance thereof can be lowered to the utmost so as toabsorb noise as quickly as possible. On the other hand, the part of thepower source wiring VL arranged along the shorter latus of therectangular chip is formed only of the second wiring layer. Since thispart of the power source wiring is made up of the second wiring layer,it can be laid in the area for arranging the peripheral circuits, andthe effect of enhancing the density of integration is achieved. Thefirst and second aluminum wiring layers are made of pure aluminum, oraluminum doped with 0.5 weight-% of Cu (copper) against migration or/and1.5 weight-% of Si (silicon) against alloy spikes. The first wiringlayer and second wiring layer of the power source wiring VL have equalwiring width dimensions, and they are short-circuited through contactholes TC formed in an inter-layer insulator film. The contact holes TCof the power source wiring VL are provided in substantially the wholeregion of the power source wiring VL in the extending direction thereof.That is, the contact holes TC are distributed so as to lower theresistance of the power source wiring VL to the utmost. The wiring widthdimension of the power source wiring VL is, for example, about 25 [μm].

Among the signal wiring leads L mentioned above, the signal wiring leadL₄ is a wiring lead (T₁) for testing the characteristics of the DRAM 1.The signal wiring lead L₅ is a reference clock signal-wiring lead whichtransmits the reference clock signal R1. The signal wiring lead L₆ is afunction pad interchange signal-wiring lead (FPIE). The signal wiringlead L₇ is a voltage limiter signal-wiring lead (V1). The signal wiringlead L₈ is a refresh signal-wiring lead (RFD). The signal wiring lead L₉is a precharge signal-wiring lead (PC). The signal wiring lead L₁₀ is asense amplifier enable signal-wiring lead (SAE). The signal wiring leadL₁₁ is a sense amplifier drive signal-wiring lead (P1). The signalwiring leads L₁₂ -L₁₅ are X-group internal address signal-wiring leads(AX8H, AX7, AX8). The signal wiring leads L₁₆ -L₁₉ are word line clearsignal-wiring leads (WC0U, WC1U, WC2U, WC3U).

The signal wiring leads L₂₀ -L₂₃ are X-group internal addresssignal-wiring leads (AX9, AX9, AXH, AXU). The signal wiring lead L₂₄ isa reference clock signal-wiring lead which transmits the CAS-groupreference clock signal C1. The signal wiring lead L₂₅ is a column enablesignal-wiring lead (CE). The signal wiring lead L₂₆ is a Y-address latchsignal-wiring lead (YL). The signal wiring lead L₂₇ is a clear modesignal-wiring lead (CM). The signal wiring lead L₂₈ is an activationsignal-wiring lead which transmits the activation signal AC of the mainamplifier MA. The signal wiring lead L₂₉ is a function set signal-wiringlead (FS). The signal wiring lead L₃₀ is a function reset signal-wiringlead (FR). The signal wiring lead L₃₁ is a data select signal-wiringlead (DS). The signal wiring lead L₃₂ is a test enable signal-wiringlead (TE). The signal wiring leads L₃₃ -L₃₅ are wiring leads for testingcharacteristics (T₂, T₃, T₄) The wiring lead L₃₆ is a redundancysignature signal-wiring lead (SiG). The signal wiring lead L₃₇ is afunction set enable signal-wiring lead (FSE).

The signal wiring leads L (L₄, L₆ -L₂₃, L₂₅ -L₂₇, L₂₉ -L₃₇) except theRAS-group reference clock signal-wiring lead (R1) L₅, CAS-groupreference clock signal-wiring lead (C1) L₂₄ and activation signal-wiringlead (AC) L₂₈ are constructed of a single-layer structure made of thesecond wiring layer (aluminum wiring). The second wiring layer has athickness greater than that of the first wiring layer. Morespecifically, the first wiring layer is formed at a thickness of, forexample, about 5000-6000 [Å] (5000 Å as a concrete instance), while thesecond wiring layer is formed at a thickness of, for example, about8000-9000 [Å] (8000 Å as a concrete instance). This is intended torender the resistance of the second wiring layer as far as possible, andalso to mitigate a step ascribable to the first wiring layer and enhancethe step coverage of the second wiring layer. These signal wiring leadsL are constructed at wiring width dimensions of, for example, about 2[μm] and at intervals of, for example, about 1.5 [μm]. In regionsunderlying the signal wiring leads L constructed of the single-layerwiring structure, different signal wiring leads can be passed, so thatthe density of integration of the DRAM 1 can be heightened byeffectively utilizing the wiring regions. By the way, these signalwiring leads L may well be constructed of the first layer of wiring.

The RAS-group reference clock signal-wiring lead (R1) L₅, CAS-groupreference clock signal-wiring lead (C1) L₂₄ and activation signal-wiringlead (AC) L₂₈, namely, the major wiring leads of the reference clocksignals are constructed of the double-layer wiring structure in whichthe first wiring layer and the second wiring layer are short-circuited,likewise to the power source-wiring leads VL. The sectional structure ofthe CAS-group reference clock signal-wiring lead (C1) L₂₄ as well as theactivation signal-wiring lead (AC) L₂₈ is shown in FIG. 13 (an enlargedsectional view of essential portions). As illustrated in FIG. 13, thefirst wiring layer AL1 and the second wiring layer AL2 areshort-circuited by contact holes TC.

Further, the first layer of aluminum wiring AL1 is provided on theinter-layer insulator film 3 through a barrier metal layer 4 which ismade of an MoSi₂ film having a thickness of, for example, 150 Å. Thus,the reaction between the aluminum wiring layer AL1 and the semiconductorsubstrate being a subbing material can be prevented. In addition, thefirst layer of aluminum wiring AL1 is overlaid with an MoSi_(x) (0<x<2)film 5 which has an Si composition ratio smaller than that of the MoSi₂film 4 and which is 200 Å thick by way of example. Owing to the factthat the MoSi_(x) film 5 of the smaller Si composition ratio is providedon the aluminum wiring layer AL1 in this manner, it is possible toprevent the corrosion of the aluminum wiring layer AL1 attributed to anelectrochemical reaction which occurs at the step of wet etching due toan intermetallic compound produced by aluminum and copper contained inthe aluminum wiring layer AL1. Furthermore, the second layer of aluminumwiring AL2 is provided on an MoSi₂ film 7 which has a thickness of, forexample, 150 Å. Thus, Mo (molybdenum) diffuses from the MoSi₂ film 7into the aluminum wiring layer AL2, whereby electromigration and stressmigration can be prevented. Accordingly, the lifetime of this aluminumwiring layer AL2 can be prolonged.

Besides, the contact holes TC are provided at predetermined intervals,for example, at intervals of 30 [μm] in a case where the wiring lengthof the reference clock signal-wiring lead is about 10 [mm]. The contactholes TC are provided in a plural number every predetermined intervalfor the purpose of preventing inferior contact and enhancing theavailable percentage of products. Since the RAS-group reference clocksignal-wiring lead (R1) L₅ is the most important, it is formed at awiring width dimension of, for example, about 5 [μm]. The contact holesTC for connecting the first wiring layer and second wiring layer of theRAS-group reference clock signal-wiring lead (R1) L₅ are provided in anumber of two in the widthwise direction of the wiring everypredetermined interval, because the wiring width dimension of thiswiring lead is greater than that of any other wiring lead. Each of theCAS-group reference clock signal-wiring lead (C1) L₂₄ and the activationsignal-wiring lead (AC) L₂₈ is formed at a wiring width dimension of,for example, about 2 [μm]. The contact holes TC for connecting the firstwiring layer and second wiring layer of each of the CAS-group referenceclock signal-wiring lead (C1) L₂₄ and the activation signal-wiring lead(AC) L₂₈ are provided in a number of two in the lengthwise direction ofthe wiring every predetermined interval, because the wiring widthdimension of this wiring lead is smaller than that of any other wiringlead. In the section shown in FIG. 13, the first wiring layer AL1 isunderlaid with the inter-layer insulator film 3 which covers the memorycell selecting MISFET and the information storing capacitor. Aninter-layer insulator film 6 is interposed between the first wiringlayer AL1 and the second wiring layer AL2. The inter-layer insulatorfilm 6 is formed with the contact holes TC. A passivation film 8 isprovided on the second wiring layer AL2.

Since the power source-wiring leads VL are constructed of thedouble-layer wiring structure as stated before and the word lines, notshown, extending in the memory cell array MARY are constructed of adouble-layer wiring structure, the double-layer wiring structure of themajor, reference clock signal-wiring leads are formed by the samemanufacturing step as that of the power source-wiring leads and the wordlines (merely by altering the pattern of a wiring forming mask), wherebythey can be constructed without increasing the number of manufacturingsteps. That is, since the double-layer wiring structure of the major,reference clock signal-wiring can be formed by the same manufacturingstep as that of the other double-layer wiring structures, amanufacturing process can be relieved in correspondence with the step offorming the double-layer wiring structure of the major, reference clocksignal-wiring. By the way, the double-layer wiring structure of the wordlines is constructed in such a way that the word line (shunting wordline) formed of the second wiring layer is connected through the firstwiring layer to the word line which is formed of the same conductorlayer as that of the gate electrode of the memory cell selecting MISFETof the memory cell. The complementary data lines and Y-select signalwiring, which extend in the memory cell array MARY, are made of thefirst layer of wiring.

In this manner, in the DRAM 1, the reference clock signal generator (RASor/and CAS) and the address-group circuits (XAB, YAB), which arerespectively arranged on the opposing shorter latus sides of therectangular chip, are connected by the reference clock signal-wiring(L₅, L₂₄ or/and L₂₈) of the double-layer wiring structure which isextended along the longer latus of the rectangular chip and isshort-circuited, whereby the resistance of the reference clocksignal-wiring is rendered lower than in case of a single-layer wiringstructure, and the propagating speed of the reference clock signal (R1,C1 or/and AC) can be heightened, so that the margins of the addresssetup time and the address hold time can be enhanced to raise theoperating speed of the DRAM 1.

FIG. 14 shows the layout of a peripheral circuit (data line prechargecircuit) portion, while FIG. 15 is an equivalent circuit diagram of theperipheral circuit shown in FIG. 14.

As illustrated in FIGS. 14 and 15, a precharge signal φ_(p) which passesthrough the wiring 9 of the peripheral circuit is delayed long by acapacitive load such as the gate capacitances of n-channel MISFETs Q₁-Q₆ constituting this peripheral circuit, and hence, an access time anda precharge time are long. Therefore, a high speed operation has beenhampered. This problem, however, can be solved in such a way that thewiring 9 has its wiring resistance lowered with a structure in which thefirst and second layers of aluminum wiring AL1 and AL2 (reinforcingwiring) connected with each other via a through hole TH are connected toa gate electrode FG made of the first layer of polycrystalline siliconwiring by way of example. In a case where the reinforcing wiring for thegate electrode FG is formed of only one layer of aluminum wiring, theresistance of the wiring can be sufficiently lowered only by increasingthe width thereof. In contrast, the use of the two layers of aluminumwiring AL1 and AL2 as stated above does not enlarge the chip size and isadvantageous. Incidentally, in FIGS. 14 and 15, symbol F denotes a fieldinsulator film for isolating the elements, and symbols D and D denotedata lines. Besides, numeral 10 indicates a wiring lead for a prechargepotential of 1/2 V_(cc), and this wiring lead is formed of the firstlayer of aluminum wiring AL1. Further, numerals 11 and 12 indicatesource and drain regions of, for example, the n⁺ -type, and theseregions are provided in self-alignment to the gate electrode FG withinan active region which is enclosed with the field insulator film F. Theexpedient thus far described is applicable also to peripheral circuitsother than the data line precharge circuit.

FIG. 16 is a layout plan of an I/O transfer circuit portion, while FIG.17 is an equivalent circuit diagram of the I/O transfer circuit portionshown in FIG. 16.

As illustrated in FIGS. 16 and 17, in the I/O transfer circuit portion,I/O lines IO1, IO1, IO2 and IO2 being access paths in the memory cellarray MARY are constructed of the structure in which the first layer ofaluminum wiring AL1 and the second layer of aluminum wiring AL2 areplaced one over the other, as in the foregoing, whereby the resistanceof the wiring can be lowered to heighten the speed of data line access.Incidentally, in FIGS. 16 and 17, symbols D1, D1, D2 and D2 denote datalines, symbols Q₇ -Q₁₀ denote n-channel MISFETs for Y-switches, andsymbol FG denotes a gate electrode which serves also as Y-switch wiringYSL.

FIG. 18 shows a cross-under portion which is defined between the firstlayer of aluminum wiring and the second layer of aluminum wiring.

As illustrated in FIG. 18, a power source-wiring lead 14 which is laidalong the shorter latus of the rectangular chip from the powersource-wiring leads L₂ and L₃ (of the double-layer structure consistingof the first layer of aluminum and the second layer of aluminum)extended along the longer latus of the rectangular chip is made of thesecond layer of aluminum wiring AL2. Parts where wiring leads L₄₁, L₄₂,. . . and L₅₀ each being made of the second layer of aluminum wiring AL2intersect the power source-wiring lead 14 are brought to a cross-understructure. More specifically, cross-under wiring leads 13 each beingmade of the first layer of aluminum wiring AL1 are formed under thesecond layer of aluminum wiring AL2 which constructs the powersource-wiring lead 14. Since, in this case, the first layer of aluminumwiring AL1 has the smaller thickness and the higher resistance asdescribed before, it is rendered wider than each of the wiring leadsL₄₁, L₄₂, . . . and L₅₀ made of the second layer of aluminum wiring AL2,so as to lower the resistance.

As stated above, it is fundamental that the second layer of aluminumwiring AL2 having the greater thickness and lower resistance is employedfor the wiring leads L₄₁, L₄₂, . . . and L₅₀ which run over longdistances, while the first layer of aluminum wiring AL1 the width ofwhich is broadened is employed for the cross-under wiring leads 13 ofshort distance. In the converse case, unless the width of the firstlayer of aluminum wiring AL1 is considerably broadened, it is difficultto lower the resistance. Therefore, the operating speed lowers due to anenlarged chip size and an increased capacitive load.

FIG. 19 shows the layout of any of CMOS inverter circuits in theperipheral circuits.

As illustrated in FIG. 19, a wiring lead 15 within the circuit block ofthe peripheral circuit is fundamentally made of the first layer ofaluminum wiring AL1, while a wiring lead L₅₁ or L₅₂ located between thecircuit blocks is made of the second layer of aluminum wiring AL2. Eachof n-channel MISFETs Q₁₁ -Q₁₃ is constructed of a source region 12, adrain region 11 and a gate electrode FG. Besides, symbols 16 and 17denote source and drain regions of, for example, the p⁺ -type, and theseregions and a gate electrode FG constitute each of p-channel MISFETs Q₁₄-Q₁₆. In this case, the first layers of aluminum wiring AL1 can bebrought into direct contact with the source regions 12, 16 and drainregions 11, 17 and the gate electrodes FG of the MISFETs Q₁₁ -Q₁₆through contact holes C. Therefore, layout rules around the contactholes C can be rendered small by making the wiring 15 within the circuitblock out of the first layer of aluminum wiring AL1 as described above.Accordingly, the layout area can be rendered small.

Effects which are attained by typical aspects of performance of thepresent invention will be briefly explained below:

The operating speed of a DRAM can be heightened.

Moreover, the stepped part of the second layer of aluminum wiringattributed to the first layer of aluminum wiring can be prevented frombreaking.

Although, in the above, the present invention has been concretelydescribed in conjunction with embodiments, it is needless to say thatthe present invention is not restricted to the foregoing embodiments,but that it can be variously altered within a scope not departing fromthe purport thereof.

By way of example, the present invention is applicable, not only to adynamic RAM employing three or more layers of aluminum wiring, but alsoto various kinds of semiconductor integrated circuit devices eachemploying at least two layers of aluminum wiring.

In addition, the present invention is applicable, not only to a DRAM asa separate device, but also to a DRAM built in a microcomputer in theshape of a rectangle.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising:(a) a memory cell array including a plurality of memory cellson a rectangular semiconductor substrate having a pair of opposinglonger sides and a pair of opposing shorter sides; (b) a firstperipheral circuit adjacent one of said shorter sides and a secondperipheral circuit adjacent the other of said shorter sides on saidsemiconductor substrate, wherein said memory cell array is locatedbetween said first and second peripheral circuits; (c) an externalterminal to be supplied with a predetermined signal other than a powersupply signal, said external terminal being located on saidsemiconductor substrate; (d) a first wiring coupling said externalterminal to said first peripheral circuit to provide said predeterminedsignal to said first peripheral circuit, wherein said first peripheralcircuit includes means for producing a predetermined output signal inresponse to said predetermined signal; (e) a second wiring coupling saidfirst peripheral circuit to said second peripheral circuit for providingsaid predetermined output signal of said first peripheral circuit tosaid second peripheral circuit, wherein said second wiring is located ata region of said substrate other than said memory cell array and extendsalong one of said longer sides in a peripheral area of saidsemiconductor substrate between said memory cell array and said one ofsaid longer sides, and (f) a third and a fourth wiring formed on bothsides of said second wiring and extending along said second wiring,wherein said second wiring comprises a first conductive layer and asecond conductive layer on said first conductive layer, said first andsecond conductive layers being electrically coupled to each other toprovide a reduced resistance to said second wiring along said one ofsaid longer sides of the substrate between said first and secondperipheral circuits, and further wherein said third and fourth wiringsare single-layer wirings each comprised either of said first conductivelayer or said second conductive layer.
 2. A semiconductor integratedcircuit device according to claim 1, wherein said first and secondconductive layers are each comprised of an aluminum layer.
 3. Asemiconductor integrated circuit device according to claim 2, whereinsaid second conductive layer has a thickness greater than that of saidfirst conductive layer.
 4. A semiconductor integrated circuit deviceaccording to claim 1, wherein each of said plurality of memory cellscomprises a switching element and an information storing element.
 5. Asemiconductor integrated circuit device according to claim 4, whereinsaid switching element is an MISFET and said information storing elementis a capacitor, and wherein said MISFET and capacitor are coupled inseries with one another.
 6. A semiconductor integrated circuit deviceaccording to claim 5, wherein said means for producing a predeterminedoutput signal in said first peripheral circuit includes a plurality ofinverters arranged so as to generate a first cock signal, as saidpredetermined output signal, from a row address strobe signal, as saidpredetermined signal, supplied to said external terminal.
 7. Asemiconductor integrated circuit device according to claim 6, whereinsaid second peripheral circuit has a plurality of inverters arranged soas to generate a second clock signal from said first clock signal.
 8. Asemiconductor integrated circuit device according to claim 7, whereinsaid first and second conductive layers are each comprised of analuminum layer.
 9. A semiconductor integrated circuit device accordingto claim 8, wherein said second conductive layer has a thickness greaterthan that of said first conductive layer.
 10. A semiconductor integratedcircuit device according to claim 1, further comprising:(f) a furtherexternal terminal to be supplied with a predetermined level of voltage,said further external terminal being arranged on said semiconductorsubstrate; and (g) a fifth wiring coupling said further externalterminal and said first and second peripheral circuits.
 11. Asemiconductor integrated circuit device according to claim 10, whereinsaid predetermined level of voltage is one of a power supply voltage anda reference voltage.
 12. A semiconductor integrated circuit deviceaccording to claim 11, wherein a part of said fifth wiring comprisessaid first conductive layer and said second conductive layer, andwherein said first and second conductive layers are electrically coupledto each other.
 13. A semiconductor integrated circuit device accordingto claim 12, wherein said first and second conductive layers are eachcomprised of an aluminum layer.
 14. A semiconductor integrated circuitdevice according to claim 13, wherein said second conductive layer has athickness greater than that of said first conductive layer.
 15. Asemiconductor integrated circuit device according to claim 1, whereinsaid third and fourth wirings are comprised of said second conductivelayer.
 16. A semiconductor integrated circuit device according to claim15, wherein said second conductive layer comprises an aluminum layer.17. A semiconductor integrated circuit device comprising:(a) a memorycell array including a plurality of memory cells on a rectangularsemiconductor substrate; (b) a first peripheral circuit and a secondperipheral circuit on said semiconductor substrate; (c) an externalterminal to be supplied with a predetermined signal other than a powersupply signal, said external terminal being located on saidsemiconductor substrate; (d) a first wiring coupling said externalterminal to said first peripheral circuit to provide said predeterminedsignal to said first peripheral circuit, wherein said first peripheralcircuit includes means for producing a predetermined output signal inresponse to said predetermined signal; (e) a second wiring coupling saidfirst peripheral circuit to said second peripheral circuit for providingsaid predetermined output signal of said first peripheral circuit tosaid second peripheral circuit; and (f) a third and a fourth wiringformed on both sides of said second wiring and extending along saidsecond wiring, wherein said second wiring comprises a first conductivelayer and a second conductive layer on said first conductive layer, saidfirst and second conductive layers being electrically coupled to eachother to provide a reduced resistance to said second wiring between saidfirst and second peripheral circuits, and further wherein said third andfourth wirings are single-layer wirings each comprised either of saidfirst conductive layer or said second conductive layer.
 18. Asemiconductor integrated circuit device according to claim 17, whereinsaid first and second conductive layers are each comprised of analuminum layer.
 19. A semiconductor integrated circuit device accordingto claim 18, wherein said second conductive layer has a thicknessgreater than that of said first conductive layer.
 20. A semiconductorintegrated circuit device according to claim 17, wherein each of saidplurality of memory cells comprises a switching element and aninformation storing element.
 21. A semiconductor integrated circuitdevice according to claim 20, wherein said switching element is a MISFETand said information storing element is a capacitor, and wherein saidMISFET and capacitor are coupled in series with one another.
 22. Asemiconductor integrated circuit device according to claim 21, whereinsaid means for producing a predetermined output signal in said firstperipheral circuit includes a plurality of inverters arranged so as togenerate a first clock signal, as said predetermined output signal, froma row address strobe signal, as said predetermined signal, supplied tosaid external terminal.
 23. A semiconductor integrated circuit deviceaccording to claim 22, wherein said second peripheral circuit has aplurality of inverters arranged so as to generate a second clock signalfrom said first clock signal.
 24. A semiconductor integrated circuitdevice according to claim 23, wherein said first and second conductivelayers are each comprised of an aluminum layer.
 25. A semiconductorintegrated circuit device according to claim 24, wherein said secondconductive layer has a thickness greater than that of said firstconductive layer.
 26. A semiconductor integrated circuit deviceaccording to claim 17, further comprising:(g) a further externalterminal to be supplied with a predetermined level of voltage, saidfurther external terminal being arranged on said semiconductorsubstrate; and (h) a fifth wiring coupled to said further externalterminal and said first and second peripheral circuits.
 27. Asemiconductor integrated circuit device according to claim 26, whereinsaid predetermined level of voltage is one of a power supply voltage anda reference voltage.
 28. A semiconductor integrated circuit deviceaccording to claim 27, wherein a part of said fifth wiring comprisessaid first conductive layer and said second conductive layer, andwherein said first and second conductive layers are electrically coupledto each other.
 29. A semiconductor integrated circuit device accordingto claim 28, wherein said first and second conductive layers are eachcomprised of an aluminum layer.
 30. A semiconductor integrated circuitdevice according to claim 29, wherein said second conductive layer has athickness greater than that of said first conductive layer.
 31. Asemiconductor integrated circuit device according to claim 17, whereinsaid third and fourth wirings are comprised of said second conductivelayer.
 32. A semiconductor integrated circuit device according to claim31, wherein said second conductive layer comprises an aluminum layer.